So, having selected Ephraim as hisbridegroom, Henry gradually walked down the aisle,while Mr. Griggs, with a fatherly smile upon hisface, shook himself and snorted at him, and pushedthe book-stall door open to reveal a range of [Pg 220]new and interesting volumes on its shelves.Henry, taking the last volume in the collection,opened it and read:
Processors are examples of an integrated circuit, with a control logic section at the front, and a core of memory cells and registers in the middle (or back). All of the memory cells and registers are connected to the control logic, with one or more bus lines to connect to the outside world. In parallel processing systems, the control logic is duplicated to use as many logic circuits as are needed to handle all of the parallel tasks; while in pipelined systems, the control logic is duplicated to handle each processor in a pipeline. The cores of memory cells and registers are clocked at a specific frequency, and the control logic at a much higher frequency to coordinate the process of fetching and storing, and to coordinate the other parts of the system. In multi-core systems, the cores of memory cells and registers are clocked separately, with each core's control logic clocked at a different frequency. In modern processors, the control logic for the pipeline may be more complex than that of the core of memory cells and registers. Most modern processor caches consist of a small chip on the same die as the processor core, with a snoop bus that can store data in memory cells. In the case of many modern microprocessors, the caches are integrated onto the same chip as the processor and are used to enhance the performance of the processor. The caches are typically segmented into 4K to 8K chunks of memory and may contain instruction and data caches.
When software is designed to run on a machine with a specific memory configuration, the program must be created to assume that this memory is available. If the program is designed to create a cache of data that can be changed from other caches and eventually to the backing store, this must be accomplished with properly synchronizing the caches and the data store. 827ec27edc